, 0.11Hz, 4.5pW gate leakage timer using differential leakage technique in 55nm DDC CMOS for small-footprint, low-frequency and low-power timing generation.
Yuya NishioAtsuki KobayashiKiichi NiitsuPublished in: ICECS (2017)
Keyphrases
- low frequency
- low power
- cmos technology
- high frequency
- nm technology
- power consumption
- high speed
- leakage current
- low voltage
- low cost
- frequency domain
- frequency band
- wavelet transform
- subband
- single chip
- image sensor
- digital signal processing
- mixed signal
- silicon on insulator
- power dissipation
- discrete wavelet transform
- vlsi circuits
- wavelet coefficients
- ultra low power
- low and high frequency
- parallel processing
- logic circuits
- filter bank
- high resolution
- spatial domain