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A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology.

Xingyuan TongDong LiuRonghua Wang
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2022)
Keyphrases
  • high speed
  • real time
  • gray code
  • binary representation
  • pairwise
  • network architecture
  • analog vlsi
  • short circuit
  • neural network
  • hardware implementation
  • data flow
  • run length
  • error correcting codes