A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA.

Henry Block Tsutomu Maruyama

Published in: FPT (2013)

Keyphrases

maximum parsimony
phylogenetic trees
hardware implementation
maximum likelihood
hardware architecture
optimal solution
cost function
particle swarm optimization
computational complexity
decision making
evolutionary algorithm
probabilistic model
simulated annealing
tabu search
structural features