A fault-tolerant deadlock-free adaptive routing for on chip interconnects.

Fabien Chaix Dimiter Avresky Nacer-Eddine Zergainoh Michael Nicolaidis

Published in: DATE (2011)

Keyphrases

fault tolerant
deadlock free
fault tolerance
routing algorithm
interconnection networks
evolvable hardware

distributed systems
high speed
low cost
routing protocol
safety critical
state machine

load balancing
cmos technology
ad hoc networks
power dissipation
concurrency control
wireless sensor networks

database systems
end to end
fine grained
shortest path
real time