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Concurrent test of Network-on-Chip interconnects and routers.

Marcos HervéPedro AlmeidaFernanda Lima KastensmidtÉrika F. CotaMarcelo Lubaszewski
Published in: LATW (2010)
Keyphrases
  • network on chip
  • power dissipation
  • input output
  • end to end
  • routing algorithm
  • high speed
  • low power
  • cmos technology