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Concurrent test of Network-on-Chip interconnects and routers.
Marcos Hervé
Pedro Almeida
Fernanda Lima Kastensmidt
Érika F. Cota
Marcelo Lubaszewski
Published in:
LATW (2010)
Keyphrases
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network on chip
power dissipation
input output
end to end
routing algorithm
high speed
low power
cmos technology