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Research Challenges for On-Chip Interconnection Networks.
John D. Owens
William J. Dally
Ron Ho
D. N. Jayasimha
Stephen W. Keckler
Li-Shiuan Peh
Published in:
IEEE Micro (2007)
Keyphrases
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interconnection networks
high speed
fault tolerant
network on chip
low cost
multistage
parallel algorithm
real time
digital libraries
graphical models
distributed systems
message passing
routing algorithm