A low-power CMOS neural amplifier with amplitude measurements for spike sorting.
Timothy K. HoriuchiThomas SwindellDavid SanderPamela AbshirePublished in: ISCAS (4) (2004)
Keyphrases
- low power
- high power
- power consumption
- high speed
- low cost
- spike trains
- spiking neurons
- network architecture
- single chip
- wide dynamic range
- cmos technology
- neuronal networks
- image sensor
- mixed signal
- low power consumption
- vlsi circuits
- wireless transmission
- logic circuits
- digital signal processing
- ultra low power
- delay insensitive
- nm technology
- vlsi architecture
- biologically plausible
- real time
- power dissipation
- cmos image sensor
- dynamic range
- gate array