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SEU reduction effectiveness of common centroid layout in differential latch at 130-nm CMOS technology.
Haibin Wang
Ao Sheng
Shiqi Wang
Jinshun Bi
Li Chen
Xiaofeng Liu
Published in:
Microelectron. Reliab. (2017)
Keyphrases
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cmos technology
low power
flip flops
power consumption
low cost
high speed
spl times
low voltage
power reduction
power dissipation
silicon on insulator
parallel processing
image sensor
mixed signal
real time