Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.
Ricardo MartinsNuno LourençoNuno HortaShenke ZhongJun YinPui-In MakRui Paulo MartinsPublished in: IEEE Trans. Circuits Syst. (2020)
Keyphrases
- power consumption
- metal oxide semiconductor
- cmos technology
- clock gating
- design concepts
- building blocks
- design principles
- design decisions
- low cost
- design process
- electronic commerce
- infrared
- power dissipation
- software tools
- design patterns
- single chip
- design considerations
- low power
- website
- parallel processing
- x ray
- high speed
- case study