Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation.
Tomasz GrzesMaciej KopczynskiPublished in: IJCRS (2019)
Keyphrases
- hardware implementation
- rough sets
- field programmable gate array
- rough set theory
- software implementation
- image processing algorithms
- fpga implementation
- hardware architecture
- efficient implementation
- signal processing
- pipelined architecture
- fpga device
- decision table
- decision rules
- information entropy
- incremental knowledge acquisition
- hardware design
- concept lattice
- fpga technology
- rough set model
- attribute set
- general purpose
- neural network
- associative memory
- continuous valued attributes
- software engineering