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Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology.
Mattia Cicalini
Massimo Piotto
Paolo Bruschi
Michele Dei
Published in:
Sensors (2022)
Keyphrases
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cmos technology
power dissipation
low power
low voltage
mixed signal
power consumption
spl times
high speed
parallel processing
data conversion
digital signal processing
low cost
analog to digital converter
cmos image sensor
design methodology
multi channel
real time
phase locked loop
case study