First steps towards SAT-based formal analog verification.

Saurabh K. Tiwary Anubhav Gupta Joel R. Phillips Claudio Pinello Radu Zlatanovici

Published in: ICCAD (2009)

Keyphrases

bounded model checking
formal methods
model checking
formal verification
formal specification
answer set programming
formal analysis
temporal logic
ai planning
real time
data sets
active learning
signal processing
sat solvers
digital circuits
analog circuits