A novel 32 bit RISC architecture unifying RISC and DSP.
Christoph BaumhofFrank MüllerOtto MüllerManfred SchlettPublished in: ICASSP (1997)
Keyphrases
- instruction set
- hardware architecture
- application specific
- low power consumption
- instruction set architecture
- computation intensive
- low cost
- real time
- floating point
- hardware implementation
- low power
- management system
- signal processing
- embedded systems
- storage devices
- digital signal processing
- database
- xilinx virtex
- connected component labeling
- neural network
- field programmable gate array
- knowledge base
- data flow
- multiresolution
- power consumption
- software architecture
- systolic array
- general purpose