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: Dynamically Reconfigurable Computing Circuit based on memory architecture.
Kaya Can Akyel
Henri-Pierre Charles
Julien Mottin
Bastien Giraud
Gregory Suraci
Sébastien Thuries
Jean-Philippe Noel
Published in:
ICRC (2016)
Keyphrases
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high speed
real time
memory management
management system
associative memory
memory size
design considerations
memory requirements
computing power
processing elements
analog vlsi
level parallelism
architectural design
limited memory
memory usage
data flow
low cost
data sets