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Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS.
Jelle Van Rethy
Hans Danneels
Valentijn De Smedt
Wim Dehaene
Georges G. E. Gielen
Published in:
IEEE J. Solid State Circuits (2013)
Keyphrases
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user interface
cmos technology
case study
real time
user experience
design principles
interface design
building blocks
missing data
high frequency
computer interface
noise model
noise level
design patterns
noise reduction
noisy images
design process
high speed
control system
neural network
data sets