Login / Signup
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology.
Hyun-Woo Lee
Ki-Han Kim
Young-Kyoung Choi
Ju-Hwan Shon
Nak-Kyu Park
Kwan-Weon Kim
Chulwoo Kim
Young-Jung Choi
Byong-Tae Chung
Published in:
ISSCC (2011)
Keyphrases
</>
low voltage
cmos technology
low power
high speed
power consumption
spl times
parallel processing
random access memory
data structure
image formation
mixed signal
embedded dram
high resolution
signal processing