A low-power bus design using joint repeater insertion and coding.
Srinivasa R. SridharaNaresh R. ShanbhagPublished in: ISLPED (2005)
Keyphrases
- low power
- high speed
- single chip
- power consumption
- low power consumption
- low cost
- vlsi architecture
- logic circuits
- digital signal processing
- power dissipation
- vlsi circuits
- power reduction
- design process
- gate array
- cmos technology
- wireless transmission
- ultra low power
- design considerations
- high power
- design methodology
- image compression