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Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.

Tetsuya YamadaMasahide AbeYusuke NittaKenji OguraManabu KusaokeMakoto IshikawaMotokazu OzawaKiwamu TakadaFumio ArakawaOsamu NishiiToshihiro Hattori
Published in: IEICE Trans. Electron. (2006)
Keyphrases
  • power consumption
  • power reduction
  • error prone
  • processor core
  • high speed
  • low power
  • duty cycle
  • embedded systems
  • database systems
  • low cost
  • data management
  • operating system