Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL.
A. Kishore KumarD. SomasundareswariV. DuraisamyT. Shunbaga PradeepaPublished in: VLSI Design (2013)
Keyphrases
- low power
- energy efficient
- logic circuits
- power consumption
- power dissipation
- single chip
- low cost
- low power consumption
- energy efficiency
- high speed
- vlsi architecture
- wireless sensor networks
- digital signal processing
- energy consumption
- sensor networks
- cmos technology
- mixed signal
- gate array
- design methodology
- power reduction
- ultra low power