Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.

P. Balasubramanian David A. Edwards William B. Toms

Published in: VLSI Design (2012)

Keyphrases

logic programming
reduction method
multiple valued
modal logic
classical logic
response time
probability theory
automated reasoning
multi valued
defeasible logic
linear logic
programmable logic
sound and complete axiomatization
data transfer
low latency
computational properties