A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems.

Eduardo de Vasconcelos Rui L. Aguiar Dinis M. Santos

Published in: ICECS (1998)

Keyphrases

high speed
expert systems
low cost
power consumption
circuit design
information systems
management system
low power
delay insensitive
analog vlsi
image sequences
computer systems
building blocks
times faster
digital circuits
vlsi circuits