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Dynamic Performance of a Chip Level Adaptive Equalizer in a UMTS High Speed Downlink Packet Access (HSDPA) Terminal.

Philip PietraskiMihaela C. BeluriRobert A. DiFazioRui YangAriela Zeira
Published in: VTC Fall (2006)
Keyphrases
  • high speed
  • low power
  • packet loss
  • low cost
  • content addressable memory
  • real time
  • high density
  • application layer
  • gigabit ethernet
  • resource allocation
  • analog vlsi