SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology.
Saeed SeyedfarajiBaset MesgariSemeen RehmanPublished in: DSD (2022)
Keyphrases
- cmos technology
- low voltage
- low power
- power consumption
- spl times
- parallel processing
- random access memory
- leakage current
- high speed
- embedded dram
- low cost
- power dissipation
- mixed signal
- image sensor
- silicon on insulator
- power reduction
- design considerations
- power system
- design process
- image processing
- computer vision