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A two stage and three stage CMOS OPAMP with fast settling, high DC gain and low power designed in 180nm technology.
Anshu Gupta
D. K. Mishra
Rajesh Khatri
U. B. S. Chandrawat
Preet Jain
Published in:
CISIM (2010)
Keyphrases
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low power
nm technology
power consumption
high speed
low cost
low power consumption
power dissipation
single chip
wireless transmission
vlsi architecture
image sensor
vlsi circuits
high power
mixed signal
cmos technology
gate array
power reduction
real time
digital signal processing
computer vision