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Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital.
Daniel León
Juan Carlos Fabero
Juan Antonio Clemente
Published in:
Microprocess. Microsystems (2024)
Keyphrases
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high speed
signal processing
empirical studies
single chip
case study
input image
low cost
statistical analysis
binary images
third party
parallel processing
high end