Formal Verification Method for Combinatorial Circuits at High Level Design.
Junji KitamichiHiroyuki KageyamaNobuo FunabikiPublished in: ASP-DAC (1999)
Keyphrases
- high level
- verification method
- design process
- low level
- high level synthesis
- logic synthesis
- design space
- formal methods
- engineering design
- conceptual model
- building blocks
- databases
- model checking
- computer aided
- database
- temporal logic
- embedded systems
- design tools
- knowledge level
- knowledge based systems
- programming language
- digital circuits
- case study
- real world