Low-power buffered clock tree design.

Ashok Vittal Malgorzata Marek-Sadowska

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)

Keyphrases

low power
power consumption
high speed
low power consumption
single chip
vlsi architecture
low cost
logic circuits
digital signal processing
gate array
mixed signal
power dissipation
design process
power reduction
vlsi circuits
ultra low power
real time
nm technology
high power