A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs.
Young-Jin JeonJoong-Ho LeeHyun-Chul LeeKyo-Won JinKyeong-Sik MinJin-Yong ChungHong-June ParkPublished in: IEEE J. Solid State Circuits (2004)