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Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).
Wei Xu
Hongbin Sun
Xiaobin Wang
Yiran Chen
Tong Zhang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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main memory
memory access
single chip
design considerations
circuit design
low cost
memory hierarchy
random access memory
data structure
high speed
design process
b tree
design methodology
design tools
physical design
modular design