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A 622/155 mbps ATM line terminator mono-chip.
Mario Diaz-Nava
Didier Belot
P. Delerue
Joseph Bulone
Published in:
ED&TC (1995)
Keyphrases
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high speed
low cost
atm networks
high density
analog vlsi
real time
line segments
single chip
physical design
vlsi implementation
low complexity
circuit design
evolvable hardware
programmable logic
priority scheduling
air traffic management