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A CMOS IF transceiver with reduced analog complexity.
Tod Paulus
Shyam S. Somayajula
Thad A. Miller
Brian Trotter
Kyong Choi
Donald A. Kerth
Published in:
IEEE J. Solid State Circuits (1998)
Keyphrases
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analog vlsi
circuit design
worst case
focal plane
computational complexity
low cost
high speed
image processing
frequency domain
power consumption
space complexity
digital circuits
delay insensitive
cmos image sensor