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A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages.
Ted E. Williams
Mark A. Horowitz
Published in:
IEEE Symposium on Computer Arithmetic (1991)
Keyphrases
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circuit design
multistage
efficient implementation
analog to digital converter
random access memory
image processing
database systems
image sequences
low cost
square root
asynchronous circuits
multiple stages