Sizing CMOS Circuits for Increased Transient Error Tolerance.
Yuvraj Singh DhillonAbdulkadir Utku DirilAbhijit ChatterjeeAdit D. SinghPublished in: IOLTS (2004)
Keyphrases
- error tolerance
- analog vlsi
- delay insensitive
- circuit design
- high speed
- vlsi circuits
- cmos technology
- floating gate
- random access memory
- focal plane
- low voltage
- power dissipation
- low power
- steady state
- low cost
- chip design
- power consumption
- data sets
- mixed signal
- cross validation
- asynchronous circuits
- support vector machine
- objective function