Formal timing analysis of gate-level digital circuits using model checking.
Qurat-ul AinOsman HasanPublished in: Microprocess. Microsystems (2024)
Keyphrases
- model checking
- digital circuits
- finite state machines
- formal specification
- formal methods
- temporal logic
- reactive systems
- model based diagnosis
- formal verification
- temporal properties
- symbolic model checking
- verification method
- reachability analysis
- model checker
- ctl model update
- automated verification
- process algebra
- finite state
- concurrent systems
- epistemic logic
- bounded model checking
- pspace complete
- linear temporal logic
- data flow
- timed automata
- transition systems
- computational complexity
- asynchronous circuits
- circuit design
- dynamic systems
- modal logic
- deterministic finite automaton