Login / Signup
A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node.
Aatmesh Shrivastava
Jagdish Nayayan Pandey
Brian P. Otis
Benton H. Calhoun
Published in:
VLSI Design (2013)
Keyphrases
</>
data sets
data collection
sensor data
data analysis
high speed
low cost
data processing
energy efficiency
location information
duty cycle