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Instruction-based high-efficient synchronization in a many-core Network-on-Chip processor.
Zhenqi Wei
Peilin Liu
Zhencheng Zeng
Jiangwei Xu
Rendong Ying
Published in:
ISCAS (2014)
Keyphrases
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high speed
network on chip
image processing
low cost
multistage
parallel processing
computer architecture
parallel architectures