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A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.
Junichi Miyakoshi
Yuichiro Murachi
Koji Hamano
Tetsuro Matsuno
Masayuki Miyama
Masahiko Yoshimoto
Published in:
IEICE Trans. Electron. (2005)
Keyphrases
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low power
systolic array
vlsi architecture
power consumption
low cost
high speed
data flow
parallel architecture
block matching motion estimation
cmos technology
hardware architecture
single chip
mixed signal
low power consumption
nm technology
signal processor
image sensor
relational databases
computer vision