Polar Codes Sequential Decoder Hardware Architecture.
Aleksei KrylovAndrey V. RashichAleksandr GelgorDmitrii K. FadeevPublished in: TSP (2019)
Keyphrases
- hardware architecture
- error control
- reed solomon
- hardware implementation
- decoding algorithm
- hardware architectures
- joint source channel
- ldpc codes
- low density parity check
- error correction
- low complexity
- error detection
- error concealment
- associative memory
- frequency domain
- processing elements
- field programmable gate array
- neural network
- real time
- distributed video coding
- turbo codes
- message passing
- coding scheme
- information systems
- block matching motion estimation