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A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation.
Xinyu Xu
Zixiang Wan
Woogeun Rhee
Zhihua Wang
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2021)
Keyphrases
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low voltage
design considerations
power line
power management
power consumption
cmos technology
multimedia
pattern recognition
leakage current