Login / Signup
A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation.
Xinyu Xu
Zixiang Wan
Woogeun Rhee
Zhihua Wang
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2021)
Keyphrases
</>
low voltage
design considerations
power line
power management
power consumption
cmos technology
multimedia
pattern recognition
leakage current