BDD decomposition for mixed CMOS/PTL logic circuit synthesis.
Yen-Tai LaiYung-Chuan JiangHong-Ming ChuPublished in: ISCAS (6) (2005)
Keyphrases
- delay insensitive
- chip design
- binary decision diagrams
- high speed
- random access memory
- decomposition method
- logic synthesis
- propositional logic
- bi level
- multi valued
- power consumption
- modal logic
- classical logic
- low cost
- asynchronous circuits
- computational properties
- power supply
- defeasible logic
- data sets
- decomposition algorithm
- probability theory
- proof theory
- wavelet packet
- analog vlsi
- decomposition methods
- image decomposition
- low power
- logic programming
- multiscale