System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
Vikram IyengarKrishnendu ChakrabartyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2002)
Keyphrases
- resource constraints
- precedence constraints
- parallel machines
- precedence relations
- scheduling problem
- ibm power processor
- batch processing
- low cost
- scheduling algorithm
- global constraints
- constraint satisfaction
- flexible manufacturing systems
- vlsi implementation
- chip design
- high speed
- power consumption
- cmos technology
- partial order
- resource utilization
- round robin
- power dissipation
- test data