Hardware Architecture for List Successive Cancellation Decoding of Polar Codes.
Alexios Balatsoukas-StimmingAlexandre J. RaymondWarren J. GrossAndreas BurgPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2014)
Keyphrases
- hardware architecture
- decoding algorithm
- error control
- hardware implementation
- parity check
- ldpc codes
- reed solomon
- low density parity check
- error correcting
- joint source channel
- error correction
- hardware architectures
- field programmable gate array
- processing elements
- reed solomon codes
- image transmission
- turbo codes
- associative memory
- block matching motion estimation
- image processing
- error detection
- machine learning
- bit rate
- pattern recognition