A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.
Yohei UmekiKoji YanagidaShusuke YoshimotoShintaro IzumiMasahiko YoshimotoHiroshi KawaguchiKoji TsunodaToshihiro SugiiPublished in: IPSJ Trans. Syst. LSI Des. Methodol. (2016)