Investigating hardware micro-instruction folding in a Java embedded processor.
Flavius GruianMark WestmijzePublished in: JTRES (2010)
Keyphrases
- instruction set
- embedded systems
- embedded processors
- memory hierarchy
- single chip
- low cost
- computer architecture
- multithreading
- ibm power processor
- computing power
- open source
- application specific
- memory management
- multi core processors
- control software
- ibm zenterprise
- floating point arithmetic
- level parallelism
- programming language
- high end
- floating point
- parallel architectures
- object oriented
- memory access
- parallel processing
- source code
- hardware and software
- database applications
- hardware software
- memory subsystem
- multimedia
- runtime environment
- java virtual machine
- dynamic random access memory
- parallel processors
- processor core
- instruction set architecture
- real time
- high speed
- micro controller
- low power
- parallel architecture
- smart camera
- input output
- java programs
- hardware implementation
- blue gene
- operating system
- general purpose processors
- general purpose
- processing elements