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An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs.
Ulrich Heinkel
Claus Mayer
Charles F. Webb
Hans Sahm
Werner Haas
Stefan Gossens
Published in:
SAMOS (2004)
Keyphrases
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high speed
low power
single chip
real time
conveyor belt
small scale
circuit design
high speed networks
frame rate
integrated circuit
flow field
web scale
high speed camera
hardware implementation
information flow
focal plane
flow patterns
optical flow