Architecture of high-speed 22-bit floating-point digital signal processor.
Yoshikazu MoriToshio JufukuMasao IidaAkira NomuraNoboru IchiuraTakao NakamuraPublished in: ICASSP (1986)
Keyphrases
- floating point
- digital signal processor
- high speed
- floating point arithmetic
- instruction set
- texas instruments
- real time
- square root
- fixed point
- multi core architecture
- real time embedded
- general purpose
- floating point unit
- sparse matrices
- low power
- fast fourier transform
- graphical models
- hardware architecture
- hardware implementation