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Design of a unified transport triggered processor for LDPC/turbo decoder.

Shahriar ShahabuddinJanne JanhunenMuhammet Fatih BayramogluMarkku J. JunttiAmanullah GhaziOlli Silvén
Published in: ICSAMOS (2013)
Keyphrases
  • design process
  • turbo codes
  • low complexity
  • single chip
  • ldpc codes
  • functional verification
  • image sequences
  • low density parity check