A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's.

Luca Sterpone Niccolò Battezzati

Published in: AHS (2008)

Keyphrases

fault tolerant
fault tolerance
power reduction
distributed systems
high speed
load balancing
high assurance
hardware design
verilog hdl
evolvable hardware
circuit design
power consumption
design considerations
power dissipation
high availability
low power
logic synthesis
data streams