CHiP: A Configurable Hybrid Parallel Covering Array Constructor.
Hanefi MercanCemal YilmazKamer KayaPublished in: IEEE Trans. Software Eng. (2019)
Keyphrases
- programmable logic
- low cost
- high speed
- parallel processing
- processor array
- systolic array
- analog vlsi
- parallel genetic algorithm
- focal plane
- parallel programming
- parallel implementation
- massively parallel
- random access memory
- parallel architecture
- multithreading
- distributed memory
- parallel computation
- level parallelism
- image sensor
- high density
- shared memory