A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL.
Peter T. BreuerCarlos Delgado KloosAndrés Marín LópezNatividad Martínez MadridLuis Sánchez FernándezPublished in: ACM Trans. Program. Lang. Syst. (1997)
Keyphrases
- hardware implementation
- hardware description language
- hardware design
- circuit design
- field programmable gate array
- fpga implementation
- hardware and software
- program synthesis
- integrated circuit
- high level
- low cost
- hardware architecture
- texture synthesis
- real time
- software implementation
- massively parallel
- parallel computing
- computing systems
- general purpose
- image processing algorithms
- high end
- personal computer
- knowledge representation
- refinement process
- programmable logic
- computer algebra
- natural language descriptions
- fpga device
- image processing